1. Field of the Invention
The present invention relates to a data processor having a pipeline processing mechanism, more particularly, it relates to the data processor such as a microprocessor including high function instructions or high function exceptional processing and interrupt processing mechanisms.
2. Description of Related Art
As a result of development of large-scale LSIs with the advance of semiconductor manufacturing techniques, also in a microprocessor, a high function instruction executing plural instructions which are prepared in firmwares is included to reduce a burden on the side of softwares and to improve the processing performances.
Since such a high function instruction necessitates complicated processings in the microprocessor, as a method of processing efficiently in the Neuman type microprocessor considering the load of the hardwares, it is efficacious to divide the high function instruction into plural processing and execute in a microprogram control mode.
Also, generally, in the data processor such as the microprocessor, the performance is improved by effecting pipeline processings and processing the plural instructions in parallel in the internal pipeline stages. The pipeline processing is advantageous in that the instructions can be apparently processed in parallel for improvement of the processing performance, since processings are divided and executed respectively in each stage. However, when loads for processings of each of the pipeline stages are not uniform, a total processing speed is restricted by the processing speed in the pipeline stage where the load is large, thus the performance can not be improved.
Accordingly, when designing the pipeline configuration, it must be taken into account that the loads for processings in each pipeline stage become uniform in response to the contents of various instructions processed by the microprocessor.
Usually, when designing the pipeline configuration of the microprocessor, a portion causing the processing speed trouble is a processing of transferring data between an external memory using an external bus. In the conventional microprocessor, by the reason that the time required for reading the data from the external bus and for writing the data into the external bus is longer as compared with the internal processing speed, the pipeline stage is provided each for these processings.
For example, in U.S. Pat. No. 4,648,034 "Busy Signal Interface between Master and Slave Processors in a Computer System". A. G. Heinger et al, the pipeline configuration of the conventional data processor is disclosed.
The conventional data processor is constituted by 6 pipeline stages, an instruction fetch stage, an instruction decoding stage, an address calculation stage, an operand fetch stage, an instruction execution stage and an operand store stage.
FIG. 1(a) to FIG. 1(e) show a flow chart of the pipeline processings of the above-mentioned conventional data processor.
The 3 pipeline stages of the instruction fetch stage, operand fetch stage and operand store stage are for executing the external bus access, and as previously described, usually in a high speed microprocessor, the delay time required for processing using the external bus is more problematic for the data processing speed than the delay time required for the internal signal processing. Therefore, the next instruction or the microinstruction is processed while the processing is executed using the external bus to reduce the comprehensive delay time.
After completing processings, 276, 277, 279 and 281 in the instruction execution stage, the processing moves to processings 283, 285, 287, 289, 291, 293 and 295 in operand store stage, wherein it is judged whether resulting operand data is written by the processing 285. When the operand data is not written, the processing in the stage is finished immediately. That is, in every cases, instructions are processed via the operand store stage.
In processings of 211, 235, 239, 269 and 281, it is judged and processed so as to proceed to the next pipeline stage after confirming that processings between respective stages have been completed.
In the Technical Report ICD87-176 "Study on CPU Architecture of a 32-bit Microprocessor TX3 based upon TRON Specifications" by Miyamori et al, Integrated Circuit Study Group, Electronic Information & Communication Society, a pipeline configuration of the microprocessor called TX3 is described.
Basically, the microprocessor TX3 comprises the seven pipeline stages of an instruction fetch stage, an instruction decoding stage, an effective address calculation stage, an address translation stage, an operand fetch stage, an instruction execution stage and an operand store stage. In the multi-stage pipeline configuration, the pipeline processings proper are processed in parallel, specifically, executing the pipeline stage of the instruction execution stage next to the instruction decoding stage to attain improvement of the performance of the microprocessor.
FIG. 2 is a schematic view showing the pipeline configuration.
As same as the example shown in FIG. 1, one pipeline stage is allocated to the processings in the operand fetch stage 302 and the operand store stage 305 to reduce a delay caused by the external bus access at processing the instructions. Also in this example, one pipeline stage is allocated to the operand store, so that for writing processing during the instruction processing, processing is always shifted to the next stage.
Furthermore, in "Architecture of the NS32532 Microprocessor" by D. Alpert et al, proc. of ICCD 1987, pp. 168 through 172, a pipeline configuration of the microprocessor called NS32532 is described. Here, the pipeline configuration constituted by four stages, 310, 312, 314 and 315, is disclosed.
FIG. 3 is a schematic view showing the pipeline configuration of the microprocessor N(S32532).
In the figure, though the operand fetch is executed together with the address calculation in the same address calculation stage 314 (3rd Stage), and the operand store together with the instruction execution in the same instruction execution stage 315 (4th Stage), a 2-word buffer 316 is provided for the operand store processing.
That is, since the writing processing is shifted to the buffer 316 for execution, the next processing can be started in the instruction execution stage. Accordingly, in this case, though there are four pipeline stages, more instructions can be processed simultaneously.
From the examples aforementioned conventionally, when the external bus access is made unconditionally respectively for the operand fetch or operand store, one pipeline stage is allocated to improve the performance of the pipeline processings. In this case, external bus access processing itself is allocated as one pipeline stage, so that when the operand fetch or operand store processing is executed, these processings were always shifted to the separate pipeline stage.
When one instruction is completed for the one microinstruction, it is not difficult to control even by the processing method described above. However, in the microprocessor including multiplex high function instructions, when plural microinstruction steps are required for one instruction, the same instruction processing may sometimes be executed simultaneously in the instruction execution and the operand fetch and operand store pipeline stages. At that time, when exception, interrupt or trap (hereinafter generally referred to an EIT) have occurred, it was complicated to control.
From such a point of view, for example, in "IMPLEMENTATION of PRECISE INTERRUPTS in PIPELINE PROCESSORS" by J. E. Smith and A. R. Pleszkun, proc. of 7th Annual International Symposium of Computer Architecture", June, 1985, pp.36-44, though difficulty of preserving the internal states for interrupt in a computer having a high grade pipeline structure is stated and a general method thereof is explained, basically, it admits necessity of a buffer for preserving the internal states. Accordingly, the more the EIT processing becomes complicated, the larger becomes an issue of processing the single instruction across the plural pipeline stages on the pipeline mechanism, to realize by the hardwares the processing for preserving the internal states at occurrence of the EIT.
In recent years, many microprocessors which execute the high grade and complicated EIT processings are developed. In such microprocessor, since the multiplex high function instructions are included, the multistage pipeline configuration of more than 5 or 6 stages is employed for speeding up these instruction processings. In such a case, because of the fact that the external bus access time of the microprocessor is slower as compared with the internal processing time, in many cases, the operand fetch and store are allocated as one pipeline stage. When the high function instruction is executed in the microprocessor, it is executed in plural microinstruction steps, so that one instruction is processed across several pipeline stages, but when the EIT occurs in this case as aforementioned, a number of hardwares are necessitated for preserving the internal states.